Substrates that encompass a silicon carbide layer are increasingly being used for standard components. Power semiconductors that block at voltages up to and above 1.2 kV, for example, are implemented as trench metal oxide semiconductor field effect transistors (trench MOSFETs) using such substrates. Power semiconductors of this kind are utilized, for example, in electric-vehicle applications, i.e. motor vehicles having batteries, for example batteries based on lithium ion cells, or in photovoltaic facilities. Microelectromechanical systems can also be implemented using such substrates. For microelectromechanical systems, the substrate can furthermore encompass a silicon dioxide layer, a silicon nitrate layer, or a silicon layer, on which the silicon carbide layer is deposited.
A trench MOSFET substrate is implemented, for example, using a substrate (n-doped 4H-SiC substrate) whose silicon carbide layer has a hexagonal crystal structure, and which is n-doped. An n-doped epitaxial silicon carbide buffer layer is disposed between the silicon carbide layer and a lightly n-doped epitaxial silicon carbide drift zone (n-drift zone).
FIG. 1 shows an implementation of this kind, according to the existing art, of a trench MOSFET 100. A heavily p-doped silicon carbide layer (p− layer) 20, which can be epitaxially grown or implanted, is disposed on the n-doped 4H-SiC substrate 10. A heavily n-doped silicon carbide layer (n+ source) 30, which likewise can be epitaxially grown or implanted and serves as a source terminal, is disposed on part of p− layer 20. A back side of 4H-SiC substrate 10 serves as a drain terminal. In addition to n+ source 30, a p+terminal (p+ plug) 40 is also implanted into p− layer 20, so that an upper side of p+plug 40 abuts against the upper side of n+ source 30, and p+plug 40 can serve to define the channel potential. p− layer 20 and n+ source 30 are each patterned by way of a cutout that is disposed above a trench with which n-drift zone 10 is patterned. The cutouts have a constant width in cross section. The trench also has a constant width except for a bottom region. The width of the trench tapers only in the bottom region as a result of the patterning, so that the trench has a cup-shaped profile in cross section. The trench is thus convex in cross section.
The trench can be coated with a gate oxide after patterning. Alternatively or additionally, heavily doped implantation (60) can occur in the bottom of the trench. A gate electrode 50 is then deposited into the trench, thus producing a vertical channel region in p− layer 20. This permits a higher packing density of parallel-connected transistors than in the case of transistors having a lateral channel region.
The patterning-related transition from the side wall of the trench to the bottom of the trench can result in very high field strengths in this region during utilization, these strengths being higher than a breakdown threshold at which the oxide layer is electrically broken down when blocked, and the component becomes damaged.